1. Field of the Invention
This invention relates to electronic systems and more particularly relates to electronic systems which include computer systems and processors having a phase-locked loop parameter modification circuit to vary parameters of the phase-locked loop.
2. Description of the Related Art
Electronic systems such as computer systems have become ubiquitous. Computer systems typically include one or more processors and a bus to connect each processor to each other, if applicable, to memory, and to various input/output devices. These components of the computer system and other computer system circuitry typically include integrated circuitry which responds to an external clock signal supplied to the processor.
Referring to FIG. 1, to provide a well-defined clock signal for clocked integrated circuitry, a phase-locked loop (PLL) circuit 100 synchronizes edges of an internal clock signal with respect to edges of an external reference clock signal (REF. CLK). A phase-frequency detector 102 detects a phase difference between the external REF. CLK signal and the output signal (INT.sub.-- CLK/N) of divide by N circuit 120, where the INTERNAL CLOCK signal frequency is N times greater than the REF. CLK signal frequency. The phase detector 102 provides an Up current control signal to the charge pump 104 to increase the frequency of INT.sub.-- CLK/N when the INT.sub.-- CLK/N signal lags the REF. CLK signal. The phase detector 102 provides a Dn current control signal to the charge pump 104 to decrease the frequency of INT.sub.-- CLK/N when the INT.sub.-- CLK/N signal leads the REF. CLK signal.
The charge pump 104 responds to the selected current control signal (Up or Dn) of the phase detector 102 by converting the current control signal into a voltage stored by capacitors C1 and C3 of loop filter 112. The charge pump 104 includes switch 109 to source current IUP to loop filter 112 and switch 110 to sink current IDN from loop filter 112. Control signal IDN maintains a fixed value resulting from connecting switch 110 to ground, and control signal IUP maintains a fixed value resulting from connecting switch 109 to a positive voltage source. Accordingly, when current IDN is provided to loop filter 112, an output voltage control signal to voltage controlled oscillator (VCO) 114 decreases, and, when current IUP is provided to loop filter 112, the output voltage control signal to VCO 114 increases.
The output voltage control signal of charge pump 104 is low pass filtered by loop filter 112 and provided to VCO 114. VCO 114 increases and decreases an output internal clock signal frequency with an increased and decreased, respectively, voltage signal from charge pump 104. The INTERNAL CLOCK signal from VCO 114 is fed back through the divide by N circuit 120 as signal INT.sub.-- CLK/N. The INTERNAL CLOCK signal is also fed to integrated circuitry 118.
The PLL 100 has several parameters which limit operational functionality. One of these parameters is the bandwidth of the PLL 100. The bandwidth of the VCO 114 refers to a maximum frequency difference between the REF. CLK and INT.sub.-- CLK/N signals which results in a phase change between the REF. C LK and INT.sub.-- CLK/N signals beyond which the PLL 100 cannot adequately adjust its output signal frequency in time to compensate for the frequency difference. Another important related parameter is the lock-time which refers to the time required by the PLL 100 to adjust its output signal frequency in response to frequency differences between the REF. CLK signal and the INT.sub.-- CLK/N signal. Another loop parameter of interest is "clock jitter" which refers to oscillation around a target frequency before being sufficiently damped to provide a well-defined clock state. Clock jitter is undesirable since it dynamically varies the time available for logic computation by integrated circuitry 118.
Increasing the bandwidth of PLL 100 to react to large frequency differences between the REF. C LK signal and the INT.sub.-- CLK/N signal may result in increased noise in a circuit incorporating PLL 100 and decreased PLL 100 resolution i.e. the ability of the PLL 100 to react to small frequency differences.